1. Field of the Invention
The present invention relates to a memory in integrated circuit form containing a device to improve the behavior of the memory in the face of different phenomena that generate leakage currents and are liable to modify the stored information elements.
Generally, a memory comprises a network of memory cells arranged in rows and columns. The cells of a same row are connected to a same word line and the cells of a same column are connected to a same bit line which enables the reading or writing of an information element in the cell located at the intersection of this bit line and the selected word line.
For certain types of memories, notably the static memories (SRAMs), the access to each memory cell is achieved by means of transistors, for example N type MOSFET transistors. During normal operation, the transistors are on or off depending on whether the cell is selected or not. Under the effect of the different disturbances (noise on the supply voltages, the creation of electron-hole pairs by impact of heavy ions on the bit lines, irradiation etc.), normally off transistors can start conducting. During the reading phases, these disturbances may place the memory cells under conditions close to writing conditions. The state of the cell may then get inverted and the stored information is then no longer the right information. This can occur especially if a large number of cells of a column are in a given state and if the cell read is precisely in the reverse state. Indeed, in this case, the leakage currents of the access transistors to the non-selected cells add up together and modify the potentials of the bit lines in a sense that tends to reverse the state of the selected cell.
2. Description of the Prior Art
In order to overcome this drawback there are ways, known to those skilled in the art, of limiting the number of memory cells per column, the effect of which is to limit the leakage current. Certain memories then contain, for example, only 64 memory cells per column.
This is a drawback for its greatly increases the number of columns having commands that are independent of one another, and this limits the storage capacities of the memories that have to be protected against these risks of disturbance of the stored information.